This invention relates to semiconductor processing and more particularly, to an improved method of manufacturing a submicron channel MOS polycrystalline silicon gate transistor.
The use of polycrystalline silicon material (polysilicon) as the gate member for a MOS transistor or as an interconnection betweem MOS transistors and other electrical components of an integrated circuit is both well-known and highly desirable in the semiconductor art. In the past, the dimensions of either polysilicon gates or interconnects were defined using standard photolithographic techniques which, of necessity, serve to limit the narrowness that can be achieved.
An early technique which was developed to define the dimensions of polysilicon gate is described in U.S. Pat. No. 3,738,880 to A. Laker which issued on June 13, 1973, entitled "METHOD OF MAKING SEMICONDUCTOR DEVICE". In this reference, a P-type dopant is diffused into a polysilicon layer through an opening in a masking layer in order to form a doped strip or line in the polysilicon layer. After removing the mask layer, only the doped portion of the polysilicon layer is selectively removed by an etchant which does not attack the doped strip or line. The net result is the production of a doped polysilicon strip or line in the desired pattern. However, the narrowness of the strip or line which is formed by the Laker technique is limited due to the fact that photolithography was used to form the opening in the masking layer and because the dopant, when diffused into a polysilicon layer, spreads laterally to form the doped line. Thus, the doped strip or line is wider than the opening in the masking layer which defined the doped line.
A recent method of manufacturing a narrow gate line is described in U.S. Pat. No. 4,124,933 to K. Nicholas, which issued on Nov. 14, 1978, entitled "METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE". In this latter reference, a gate is formed having a relatively narrow line by laterally diffusing a boron dopant into a portion of a polysilicon layer at the edges thereof. This is accomplished by providing a silicon body with a relatively thick layer of silicon dioxide which will subsequently form the gate oxide for the device. Thereafter, a layer of polysilicon is applied on top of the gate oxide followed by successive layer of silicon nitride and a masking oxide. Using the masking oxide as a mask for the nitride layer, the nitride layer is etched to expose portions of the surface of the polysilicon layer and the now exposed portions of the surface of the polysilicon layer are then etched down to the gate oxide layer. The next step is the diffusion of boron into the exposed edges of polysilicon after which the nitride layer, and the undoped polysilicon layers are removed by suitable etchants.
One difficulty that arises in the Nicholas process resides in the fact that Nicholas requires a relatively thick layer of gate oxide of the order of about 0.1 micron (1,000 angstroms) thick. The need for the thick oxide arises when, for example, a boron nitride source is used for the diffusion of boron into the polysilicon layer. In addition to doping the edges of the polysilicon layer, a boron doped oxide is also formed on the exposed gate oxide layer. Thereafter, when removing the boron doped oxide from the surfaces, it is extremely likely that portions of the gate oxide layer will also be etched, thus exposing the semiconductor body. To prevent this from happening and also to prevent the boron from doping the body of semiconductor material through the opening, a thick oxide layer, of the order of about 1,000 angstroms is thus necessary. However, this is undesirable in situations where it is necessary to form the gate oxide to a thickness of about 100-200 angstroms or about one order of magnitude thinner than Nicholas.
The need for gate insulators having thicknesses in the 100-200 angstroms rage, for example, is described in U.S. Pat. No. 4,162,504 to S. T. Hsu, which issued July 24, 1979 and entitled "FLOATING GATE SOLID-STATE STORAGE DEVICE" and in Ser. No. 946,722, filed Sept. 28, 1978 and entitled "ELECTRICALLY PROGRAMMABLE FLOATING GATE READ ONLY MEMORY DEVICE AND METHOD FOR MAKING SAME". Still another floating gate device that would utilize a gate insulator having a thickness of about 100-200 angstroms is U.S. Application Ser. No. 086,313, filed Oct. 17, 1979 and entitled "IMPROVED GATE INJECTED FLOATING GATE AND MEMORY DEVICE" in which a novel floating gate device has charge injected into the floating gate from the control gate in order to maintain the integrity of the gate insulator.